IBM breaks the 1nm barrier with 3D Nano Stack chips

For years, industry watchers have been preparing to read the last rites for Moore’s law. As transistor features shrink down to the size of single atoms, squeezing more logic onto a flat slice of silicon was bound to hit a hard physical wall.

IBM’s response? When you run out of land, you build high-rises.

IBM unveiled what it calls the world’s first sub-1 nanometer chip technology, stepping firmly into the 0.7-nanometer—or 7-angstrom—node. The breakthrough is powered by a new transistor architecture dubbed Nano Stack.

Going vertical when the floor runs out

The semiconductor industry’s current cutting edge relies on nanosheet designs originally pioneered by IBM. Nano Stack takes that concept and pushes it into the third dimension as the industry’s first 3D, nanosheet-based architecture.

Instead of just shrinking horizontal dimensions, Nano Stack vertically stacks and staggers transistors using sequential 3D integration. Crucially, each stacked layer can use different material combinations, allowing engineers to optimize the power and performance of individual transistors independently.

The result is staggering density. IBM managed to pack nearly 100 billion transistors onto a chip the size of a fingernail, roughly doubling the density of its own 2nm node introduced back in 2021.

Performance claims are equally aggressive: the technology is projected to offer up to 50 percent more performance or 70 percent greater energy efficiency compared to 2nm chips. At the VLSI 2026 conference, IBM researchers also showed that Nano Stack delivers a 40 percent scaling reduction in SRAM—a critical win for data-hungry AI workloads choked by memory constraints.

From lab bench to High NA EUV

Radical chip concepts often look great on paper but collapse in the fab. IBM made sure to bring real hardware evidence.

Researchers experimentally validated the architecture through ultra-thin dielectric bonding in CMOS integration, demonstrated dual-channel engineering, and produced a functioning CMOS inverter that switches properly. In short: it is physically buildable, and it actually crunches logic.

The work is taking place at IBM’s research center in Albany, New York, alongside an ecosystem of heavyweights including Lam Research, Tokyo Electron, and SCREEN. The facility is set to deploy ASML’s High NA EUV lithography tool, which is considered essential for printing circuitry at these extreme dimensions.

Jay Gambetta, Director of IBM Research, noted that Nano Stack represents a fundamental reinvention of how chips are built, claiming it lays out a roadmap for at least another decade of scaling.

Why it matters

In our view, this announcement matters most because it blows open a psychological ceiling for hardware engineers.

Node names at 0.7nm or 7 angstroms are marketing terms rather than literal physical dimensions, but the underlying engineering hurdles are very real. By demonstrating that true 3D sequential stacking works with heterogeneous materials, IBM proves that approaching atomic limits does not mean compute gains have to grind to a halt.

For enterprise AI and hyperscalers, a projected 70 percent power reduction coupled with 40 percent denser SRAM is music to their ears. Energy consumption has become the hard ceiling for model scaling, and structural breakthroughs like this will be required to keep frontier training and inference economically viable.

That said, temper your immediate expectations. IBM is an R&D powerhouse, not a high-volume foundry. Commercializing this architecture will take years of brutal manufacturing iteration, thermal mitigation, and yield optimization by foundries like TSMC, Intel, or Samsung.

Even so, IBM just proved that the atomic wall has a staircase. Moore’s law lives to fight another day.